As technology advances, the importance of logic scaling continues to grow. However, traditional approaches to logic scaling are no longer effective due to lithographic limitations. In recent years, double and triple patterning techniques have been implemented for metal1 layer structures to mitigate the effects of such limitations by enabling metal1 layer structures to be formed closer to each other. However, the use of additional patterning processes also have their limits with respect to logic scaling as a result of increased complexities, high costs, and reliability issues that may be associated with further patterning (e.g., quadruple patterning) of these metal1 layer structures.
A need therefore exists for other logic-scaling-related constructs that do not rely on further patterning of metal1 layer structures, and enabling methodology.